Recently, the semiconductor circuit devices such as ICs, LSIs, etc. have been developed markedly owing to the element microminiaturization technique represented by scaling technique. In the generation prior to 1 .mu.m until now, the devices have been microminiaturized by scaling only the element dimensions with the supply voltage kept at a constant value (e.g., 5 V). In the recent submicron generation, however, it has become difficult to maintain the supply voltage at only 5 V. In other words, it has become impossible to disregard a decrease in the breakdown voltage due to a decrease in thickness of the gate oxide film or a decrease in hot carrier breakdown voltage due to a decrease in length of the gate. On the other hand, the current consumption increases more and more with increasing number of elements per chip and therefore the quantity of heat generated by a single chip increases, in spite of the fact that there exists a strong demand of lower power consumption in the case of a portable device, in particular. Therefore, the packaging technique has now approached a limit. As described above, a lower supply voltage is required more and more from the standpoints from both the element makers and users. In practice, however, it is still difficult to change the supply voltage from 5 V to 3 V, for instance. This is because all the ICs included in a system must be activated by 3 V and additionally there exist some ICs (e.g., analog ICs) not suitable for low voltage. Accordingly, a system in which 3 V and 5 V supply voltages are mixed has been inevitably required, prior to realization of a system activated by only the 3 V supply voltage. The present invention relates to an interface disposed between integrated circuits operative by different supply voltages, and provides a semiconductor integrated circuit device used with integrated circuits to which a lower supply voltage is required (e.g., microcomputer, memory device, general purpose logic circuit, ASICLSI, etc.).
FIG. 14 shows an ordinary input and output circuit for a semiconductor integrated circuit device. In the case of the input and output circuit for an integrated circuit (LSI) of CMOS structure, the input and output circuit is generally composed of CMOS circuits in the same way as the internal circuit elements. The input and output circuit as shown in FIG. 14 is provided with an output buffer 2 and an input buffer 3 both connected to an input and output terminal 1. This input and output terminal 1 is referred to as a pad electrode on the semiconductor substrate. A number of pad electrodes are arranged on the periphery of the semiconductor substrate. Between the buffers 2, 3 and the input and output terminal 1, a protective circuit is connected to protect the circuit from an electrostatic discharge applied from the outside. This protective circuit is composed of a resistor R1 and a diode D1. The output buffer 2 is composed of an N channel MOS FET (referred to as NMOS transistor, hereinafter) Q1 and a P channel MOS FET (referred to as PMOS transistor, hereinafter) Q2. The input buffer 3 is composed of an NMOS transistor Q3 and a PMOS transistor Q4. A signal A is applied to the PMOS transistor Q2 of the output buffer 2 and a signal B is applied to the NMOS transistor Q1 of the output buffer 2. The input and output status of this input and output circuit can be listed in Table 1 as follows:
TABLE 1 ______________________________________ A B Q1 Q2 INPUT/OUTPUT STATUS ______________________________________ L L OFF ON H OUTPUT H H ON OFF L OUTPUT H L OFF OFF HIGH IMP. INPUT ______________________________________
Table 1 above indicates that the operation is composed of three input and output statuses. That is, when both the signals A and B are at a low ("L") level, the NMOS transistor Q1 is turned off and the PMOS transistor Q2 is turned on, so that the input and output status is at a high ("H") output status. When both signals are at a high ("H") level, Q1 is turned on and Q2 is turned off, so that the input and output status is a low ("L") output status. When the signal A is at a high ("H") level and the signal B is at a low ("L") level, both Q1 and Q2 are turned off, so that the input and output status is at a high ("H") impedance input status.
The input and output circuit of the CMOS circuit as described above is widely used for the semiconductor integrated circuits. However, it is not allowed to apply a voltage lower than the ground voltage 0 V or higher than the supply voltage Vcc. For instance, if a voltage higher than Vcc is applied, the PN junction formed at the drain of the PMOS transistor Q2 is biased in the forward direction, so that a large current flows from the input and output terminal 1 to the supply voltage Vcc. Therefore, the voltage applied to the input and output terminal 1 is standardized so as to be limited within a range higher than (ground voltage 0 V +0.5 V) and lower than (supply voltage Vcc +0.5 V).
With the advance of the microminiaturization and higher integration of the integrated circuit of CMOS structure, however, it has become difficult more and more to conform to the above-mentioned limit. In the case of the CMOS-LSI using MOS transistors each with a gate length of 0.5 .mu.m or less, for instance, it has been proposed that the ordinary supply voltage of 5 V is to be lowered to about 3 V in order to prevent the element reliability from being deteriorated due to an increase in the electric field of the internal elements, as disclosed in JEDEC STANDARD 8-1, 1984. In addition, it is desirable to reduce the supply voltage; that is, to reduce the signal amplitude from the standpoints of reduction of noise generated whenever the input and output circuit of the integrated circuit is switched. However, since the CMOS circuits are usually connected to other CMOS-LSIs of various functions so as to construct a system, without being used independently as an integrated circuit, all the CMOS LSI are not necessarily operative on the basis of only a low supply voltage; that is, there exist cases where a plurality of integrated circuits activated by supply voltages of 3 V and 5 V are mixed with each other. Therefore, in the case where a high level voltage of 5 V is applied to the input and output circuit of the integrated circuit of the supply voltage 3 V, since the PN junction is biased in the forward direction as already explained and thereby the elements may be broken down, it is impossible to use the conventional input and output circuit as it is.
FIG. 15 is another conventional input and output circuit which is provided with an interface circuit between two circuits of different supply voltages, as disclosed in Japanese Patent Application No. 3-3827. This input and output circuit is provided for the lower supply voltage side integrated circuit of the integrated circuits of different supply voltages. In FIG. 15, a push-pull circuit 2 is composed of an NMOS transistor Q1 and a PMOS transistor Q2 of the ordinary output buffer circuit. Further, an NMOS transistor of depletion type (referred to as D transistor, hereinafter) having a gate connected to a supply voltage is connected between the push-pull circuit 2 and an input and output terminal (pad) 1. The depletion type transistor is a transistor which is normally turned on or whose threshold value (Vthd) is negative so as to constitute an interface circuit. In this conventional interface circuit, there exists a problem in that the threshold value Vthd of the D transistor has no margin, which is explained in further detail hereinbelow on the assumption that the supply voltage is 3.3 V .+-.0.3 V; and the inputted external signal amplitude is 5 V.
In FIG. 15, the D transistor effects two contradictory operations. One is not to transmit the externally applied 5V to the internal side as much as possible; that is, to suppress the internal Va as low as possible, when the supply voltage of 5 V is inputted. The other is to transmit the internal voltage Vcc to the external side as much as possible; that is, to secure the signal amplitude of Vout, when the supply voltage Vcc is outputted. In this case, the circuit elements are broken down if the input voltage Va is not suppressed lower than an oxide film breakdown voltage of about 3.6 V as shown by (1) and (4) in FIG. 15 and lower than a forward bias voltage of (Vcc+0.3 V) at the PN junction of the PMOS transistor as shown by (2) in FIG. 15. On the other hand, it is necessary to secure the output voltage Vout as shown by (3) in FIG. 15 at the voltage of Von=2.7 V of the TTL. FIG. 16 shows the bias status of the D transistor. In FIG. 16, when 5 V is inputted, 5 V is applied to the pad 1 of the source side and Vcc is applied to the gate thereof, so that Va is Vcc-Vthd (Vcc), where the second term is a threshold value Vthd of the D transistor to which a back gate voltage Vcc is applied. On the other hand, when Vcc is outputted, the voltages of the source and the drain are reversed and Vcc is applied to the source and the gate thereof, so that Vout is Vcc-Vthd (Vcc).
In summary, in the conventional input and output circuit shown in FIG. 15, it is necessary to use the same element at the same bias conditions and further to decrease the inputted voltage Va as low as possible and increase the outputted voltage Vout as high as possible. FIG. 17 shows these conditions as a margin map of the conventional circuit, in which the worst cases are shown with the supply voltage Vcc taken on the abscissa and with the input voltage Va or the output voltage Vout taken on the ordinate. In other words, in the worst case, Va must be less than the breakdown voltage 3.6 V of the oxide film at Vcc=3.6 V. Therefore, the threshold voltage of the D transistor at the time when the back gate voltage Vcc is applied is Vthd (3.6 V).gtoreq.0 V. 0n the other hand, in the worst case, Vout must be higher than Von=2.7 V at Vcc=3 V. Therefore, the threshold voltage Vthd (3.0 V).gtoreq.0.3 V. FIG. 18 shows a margin of the threshold value of the D transistor, in which the back gate voltage V.sub.BG or VCC is taken on the abscissa and the threshold voltage Vthd is taken on the ordinate. In FIG. 18, the curve A indicates the characteristics of the Vthd required to secure the output voltage Vout at a predetermined value in dependence upon the back gate voltage V.sub.BG, and the curve B indicates the characteristics of the Vthd required to secure the input voltage Va in dependence upon the back gate voltage V.sub.BG. In FIG. 18, when Vcc=3 V. the allowable margin (difference) of the threshold voltage of the D transistor is about 0.5 V. This value of about 0.5 V is not satisfactory when the manufacturing dispersion and the temperature range at which the operation is guaranteed are taken into account. Further, it is impossible to widen the operation supply voltage range in the case of the conventional input and output circuit.